FROMLIST: power: supply: qcom_battmgr: fix battery chemistry strncmp … - #942

Define pinctrl definitions to enable camera master clocks on glymur.

Signed-off-by: Nihal Kumar Gupta <nihalkum@qti.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

Define ov08x40 on cci1_i2c1. The RGB sensor is connected to
CSIPHY4 in four lane mode.

Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

…glymur

Add an IMEM on glymur which falls back to mmio-sram and define the
PIL relocation info region as its child, for post mortem tools to
locate the loaded remoteprocs.

Link: https://lore.kernel.org/lkml/20260424-glymur-imem-v5-2-18ede63cf063@oss.qualcomm.com/#r
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

Without this property the scheduler treats all cores as equal.
Values derived from performance measurements at 825.6 MHz:
- M-class cores (cpu0-cpu5, oryon-2-2): capacity-dmips-mhz = 1024
- L-class cores (cpu6-cpu17, oryon-2-1): capacity-dmips-mhz = 1372
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

… devices

Add label properties to TPDM and CTI nodes in the glymur device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.

Link: https://lore.kernel.org/all/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com/
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

The QCB (Qualcomm Compute Board) is a board built on the Qualcomm
Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor
suitable for compute workloads, power measurements and oscilloscope-based
hardware validation.

Add a compatible for this board.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

The QCB (Qualcomm Compute Board) is a board built on the Qualcomm
Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor
suitable for compute workloads, power measurements and oscilloscope-based
hardware validation.

Add initial device tree support for it.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

The Mahua QCB (Qualcomm Compute Board) is a board built on the Qualcomm
Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor.
Unlike the CRD, the QCB is suitable for compute workloads, power
measurements and oscilloscope-based hardware validation.

Add a compatible for this board.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

Add initial device tree support for the Mahua QCB. The QCB (Qualcomm
Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core
variant of the Glymur QCB in an open form factor. Unlike the CRD, the
QCB is suitable for compute workloads, power measurements and
oscilloscope-based hardware validation.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>

Reserve memory region for audio PD dynamic loading and remote heap
requirements. Add the required VMID list for memory ownership
transfers.

Link: https://lore.kernel.org/all/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com/
Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Signed-off-by: Vinayak Katoch <vinayak.katoch@oss.qualcomm.com>

…PHY on Glymur

The PCIe PHYs on Glymur require a reference voltage provided by REFGEN,
which in turn is powered by two LDOs.

Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and
vdda-refgen1p2 supplies for each PCIe PHY node.

Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

The TCSR clkref_en clocks gate the QREF block which provides reference
clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF
and refgen blocks on the CRD board.

Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

Mahua has a different QREF topology from Glymur. Override the TCSR
compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required
LDO supplies on the CRD board.

Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk
from the CXO0 pad directly and requires no QREF clkref_en voting. Hence,
point its ref clock at RPMH_CXO_CLK.

Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

…R for glymur-qcb

Wire up the required LDO supplies on the QCB board.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

…R for mahua-qcb

Wire up the required LDO supplies on the QCB board.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>

… voltage for SD-card

SD cards may need 1.8v VDDIO also to be supported, to accommodate this
requirement reduce the min voltage to 1.8v for `vreg_l2b_e0` which
supplies to VDDIO pin of SD card.

NOTE - Since this SD card is the only client on this regulator, this
change should not have any side effect on any other clients.
moreover, SD card driver takes care to explicitly vote for the
regulator voltage based on the SD card detection sequence.

Also for stable operation of the SD card increase VDD voltage
supplied by `vreg_l9b_e0` to 2.96v.

Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260702094056.3755467-2-mchunara@oss.qualcomm.com/
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>

Document the Glymur-specific SDHCI compatible in the sdhci-msm binding.
Use "qcom,sdhci-msm-v5" as the fallback compatible for the MSM SDHCI v5
controller used on Glymur.

Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260703-loutish-stimulating-hummingbird-aada5e@quoll/
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>

Add support for SD card on Glymur SoC and enable the required pinctrl
configurations.

Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com>
Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com>
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260702094056.3755467-4-mchunara@oss.qualcomm.com/
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>

Enable SD card for Glymur CRD platform. Configure the vmmc/vqmmc
regulators and gpio-based card detection for the platform.

Co-developed-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com>
Signed-off-by: Sachin Rathore <sachin.rathore@oss.qualcomm.com>
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260702094056.3755467-5-mchunara@oss.qualcomm.com/
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>

The traceNoC node is the system-level Aggregator TNOC, so it must own a
valid ATID that tags the whole aggregation path. It was marked compatible
with "qcom,coresight-itnoc", an Interconnect TNOC, which is never assigned
an ATID. As a result the aggregator had no trace ID and could not tag the
merged trace.

An Interconnect TNOC is a subsystem-level aggregator: it merges trace from
the ATB sources within its subsystem (TPDMs and other ATB masters) and
forwards the combined stream to the system-level Aggregator TNOC. It
carries no ATID of its own, because the Aggregator TNOC downstream in the
path already owns the ATID.

Switch the node to "qcom,coresight-tnoc" so it is described as the
Aggregator TNOC it is and is assigned a system trace ID. Rename the node
to "tn" and use the "apb_pclk" clock name as required by the Aggregator
TNOC binding.

Link: https://lore.kernel.org/all/20260710-fix-tracenoc-probe-issue-v6-5-41eb36fef8d9@oss.qualcomm.com/
Fixes: 1f7d0c4 ("arm64: dts: qcom: glymur: add coresight nodes")
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>

Embedded Trace Router(ETR) is working as a DDR memory sink to collect
tracing data from source device and the CTCU device serves as the
control unit for the ETR device.

Link: https://lore.kernel.org/all/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com/
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>

…ature Sensor

Document the Temperature Sensor (TSENS) on the Qualcomm Maili SoC.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Haritha S K <haritha.k@oss.qualcomm.com>
Link: https://patch.msgid.link/20260619-b4-maili-upstream-3-v2-1-e54516c37022@oss.qualcomm.com

The OS PDC DRV register window on eliza spans 0x10000 bytes. Reduce
the size of the first reg entry from 0x40000 to 0x10000.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527094333.2311731-25-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

…board

Document the compatible strings for the Qualcomm Eliza CQS
System-on-Module (SoM) and its EVK board.

The SoM is populated with a CQ7790S Eliza variant, PMICs, LPDDR and
eMMC. The SoM is then connected to the EVK base board, which provides
a multitude of connectors for peripherals.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

The Eliza CQS (CQ7790S) System-on-Module is designed to be connected to
an Eliza EVK base board. The SoM provides the SoC, PMICs, LPDDR and eMMC,
while the EVK base board provides connectors for a multitude of
peripherals.

Add the Eliza CQS SoM DTSI so it can be included by the EVK board DTS.
Describe the regulators and board clocks, enable eMMC support through
SDHC1, specify the ADSP firmware and enable the ADSP remoteproc.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

The Eliza CQS EVK board combines the CQ7790S-based (Eliza) SoM with the
common Eliza EVK base board, which provides connectors for different
peripherals.

Add a common Eliza EVK dtsi for the base board bits that can be reused
alongside other Eliza SoM variants. Then, add the final Eliza CQS EVK dts,
including the CQS SoM and common EVK dtsi.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Both the CQS SoM and the MTP have the following array of PMICs:
PMK8550, PM7550, 2x PM8550VS, PMIV0102 and PMR735D.

Since on Eliza there is already support for SPMI multi-master,
it is necessary to duplicate the devicetree description for each
of these PMICs, due to the SPMI bus index and address.

So add a new Elize specific dtsi for each of these PMICs and include
all of them in both the CQS SoM and MTP board dts.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Add the device nodes for the multimedia clock controllers (cambistmclkcc,
camcc, videocc, gpucc) for Qualcomm Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260525-eliza_mm_cc_v2-v5-7-a1d125619a5a@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2
(PCIe1). Add PCIe controller and PHY nodes for both instances, and update
the GCC clock references to use the newly added PHY nodes instead of
placeholder zeros.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

# Conflicts:
#	Makefile

# Conflicts:
#	arch/arm64/boot/dts/qcom/monaco-evk.dts
#	arch/arm64/boot/dts/qcom/monaco.dtsi

# Conflicts:
#	Makefile

# Conflicts:
#	arch/arm64/boot/dts/qcom/Makefile
#	arch/arm64/boot/dts/qcom/talos.dtsi

# Conflicts:
#	arch/arm64/boot/dts/qcom/qcs8300-ride.dts
#	drivers/bluetooth/hci_qca.c
#	drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

# Conflicts:
#	drivers/firmware/qcom/Kconfig
#	drivers/firmware/qcom/Makefile

# Conflicts:
#	drivers/dma/qcom/bam_dma.c
#	drivers/misc/fastrpc.c
#	sound/soc/qcom/qdsp6/q6prm.h
#	sound/soc/qcom/sc8280xp.c

# Conflicts:
#	Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml

…emory and SMMU mappings"

This change have introduced an issue on multimedia builds where AudioRecord
is broken on monaco-evk board.

[  153.325884] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 19
[  153.335982] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on SEC_MI2S_TX
[  153.348489]  MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture
[  153.357875]  MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed

Revert the change for now, to fix the issue.

This reverts commit cd0f5c6.

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

This is causing bootup crash on hamoa-iot-evk as the dependency
firmware is still not present.

[    8.804602][  T243] pstate: 41400005 (nZcv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[    8.804603][  T243] pc : spi_geni_init+0x44/0x858 [spi_geni_qcom]
[    8.804609][  T243] lr : spi_geni_init+0x38/0x858 [spi_geni_qcom]
[    8.804611][  T243] sp : ffff8000821eb7f0
[    8.804612][  T243] x29: ffff8000821eb7f0 x28: 0000000000000000 x27: 000000000000000c
[    8.804614][  T243] x26: ffffd1d854b495f8 x25: ffff0008129508e0 x24: ffffd1d854b49638
[    8.804616][  T243] x23: ffff800082d54068 x22: ffff0008124a1000 x21: ffff000802ed2010
[    8.804618][  T243] x20: a89ad1d854b41a5c x19: ffff0008124a16c0 x18: ffffd1d874482008
[    8.804620][  T243] x17: ffffd1d874481ff0 x16: ffffd1d872769b48 x15: 0000000000802c80
[    8.804622][  T243] x14: ffff8000821eb130 x13: 0000000160000008 x12: 0000000000000010
[    8.804624][  T243] x11: 0000000000000000 x10: ffff00080d8ee868 x9 : ffffd1d872b9c9c4
[    8.804626][  T243] x8 : ffff8000821eb698 x7 : 0000000000000000 x6 : 0000000000000001
[    8.804628][  T243] x5 : ffffd1d87402b000 x4 : ffffd1d87402b460 x3 : 0000000000000000
[    8.804630][  T243] x2 : ffff00080fc94d40 x1 : ffff00080fc94d40 x0 : 0000000000000000
[    8.804632][  T243] Call trace:
[    8.804633][  T243]  spi_geni_init+0x44/0x858 [spi_geni_qcom] (P)
[    8.804636][  T243]  spi_geni_probe+0x30c/0x3f0 [spi_geni_qcom]
[    8.804638][  T243]  platform_probe+0x64/0xa8
[    8.804642][  T243]  really_probe+0xc8/0x3f0
[    8.804645][  T243]  __driver_probe_device+0x1b4/0x1f0
[    8.804647][  T243]  driver_probe_device+0x44/0x128

Revert the commit for now, to resolve bootup issue.

This reverts commit 181bef7.

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

…emory and SMMU mappings"

This change have introduced an issue on multimedia builds where AudioRecord
is broken on lemans-evk board.

[  840.168044] q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 21
[  840.178229] q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on TERT_MI2S_TX
[  840.190901]  MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture
[  840.200277]  MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed

Revert the change for now, to fix the issue.

This reverts commit f75b90a.

This change have introduced a regression on Shikra board,
wherein Rx on UART Shell is stuck, and no input is accepted.

Issue: qualcomm-linux#921

Revert the change for now, to fix the issue.

This reverts commit 6a36c4b.

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

Adding merge log file and topic_SHA1 file

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>

…org/pub/scm/linux/kernel/git/torvalds/linux.git

tech/bsp/clk d8a14b9 30
tech/bsp/devfreq 4809534 7
tech/security/firmware-smc de7413c 6
tech/bsp/soc-infra ff6ff7b 22
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 39a86aa 13
tech/bus/peripherals fedd8c6 6
tech/bus/pci/all 9f6650a 43
tech/bus/pci/phy 66e44c2 14
tech/bus/usb/dwc 9dd47ad 3
tech/bus/usb/phy c3aa7d5 35
tech/debug/hwtracing 27d6059 23
tech/pmic/misc 5d2c2d7 12
tech/mem/iommu cdc9e80 9
tech/mm/audio/all 88b8f29 8
tech/mm/camss 3bcce10 47
tech/mm/drm 9e407ef 68
tech/mm/fastrpc 7afcba9 12
tech/mm/video d5379b4 122
tech/mm/gpu 0b8d9f4 7
tech/mproc/rpmsg 55dc464 1
tech/net/ath 900d237 29
tech/net/bluetooth 33aa6a3 1
tech/pm/power bb88701 13
tech/pm/thermal 9fdfd80 12
tech/security/crypto 1f60c0a 23
tech/security/ice beabac0 9
tech/storage/all cef1b3c 5
tech/all/dt/qcs6490 740676b 27
tech/all/dt/qcs9100 0a48d61 92
tech/all/dt/qcs8300 5cb63a5 25
tech/all/dt/qcs615 9a58c35 9
tech/all/dt/agatti c828f10 1
tech/all/dt/eliza ddb736b 23
tech/all/dt/hamoa 2e751da 42
tech/all/dt/glymur d288220 52
tech/all/dt/kaanapali 625c171 21
tech/all/dt/pakala 960924d 13
tech/all/config 90a294d 72
tech/overlay/dt b895d0e 78
tech/all/workaround a2ced88 20
tech/mproc/all 104969c 2
tech/noup/debug/all 80bf7fe 26
tech/hwe/unoq a2d85fe 4
early/hwe/shikra/drivers b19d2ec 184
early/hwe/shikra/dt dd90d88 130

…length

The battery_chemistry field is a 4-byte array without guaranteed null
termination. Using BATTMGR_CHEMISTRY_LEN (4) as the strncmp length for
3-character string literals implicitly requires chemistry[3] == '\0',
which may not hold. Use 3 instead to match only the significant bytes.

Link: https://lore.kernel.org/all/20260812-fix-qcom-batt-chemistry-strn-v1-1-458545e02641@oss.qualcomm.com/
Signed-off-by: Tingguo Cheng <tingguo.cheng@oss.qualcomm.com>